In a power control device which includes a power control circuit that controls power and a circuit control unit that controls the power control circuit, the power control circuit including a power setting field for setting a predetermined value of power, a power control, unit that controls power, and a control effective field for setting an effective state indicating that the power control unit is in a state of executing control of power, the technique of performing the following control is known (see, for example, Patent Document 1). Specifically, when the control effective field is set in the effective state, the power control unit executes control of power so that when a predetermined operation to the power control circuit is executed from the outside of the power control circuit, the circuit control unit sets the control effective field into the effective state, and stops the predetermined operation until the power reaches the value of the power set in the power setting field.
Further, in an electronic device which includes a power supply unit, a clock signal generation unit, an arithmetic processing circuit including processing core unit, and a power saving control unit that controls shift processing between a normal mode and a power saving mode, a technique of performing the following control is known (see, for example, Patent Document 2). Specifically, the power saving control unit validates a clock frequency down signal to the clock signal generation unit when shifting to the power saving mode, and validates a voltage down signal to the power supply unit after a lapse of a first time. Then, when the clock frequency down signal is validated, the clock signal generation unit gradually changes the frequency of the clock to be supplied to the arithmetic processing circuit from a first frequency to a second frequency lower than the first frequency. Further, when the voltage down signal is validated, the power supply unit decreases the voltage to be supplied to the arithmetic processing core unit of the arithmetic processing circuit from a first voltage to a second voltage lower than the first voltage.
Patent Document 1: Japanese Laid-open Patent Publication No. 2003-150283
Patent Document 2: Japanese Laid-open Patent Publication No. 2008-107962
There is a known processor which controls, by a frequency parameter set in a PLL (Phase Locked Loop) setting register, the frequency of a clock signal oscillated by a PLL, and controls the voltage inside the processor by a voltage parameter set in a voltage control register. In recent years, with increase in the number of processors mounted in an information processing device such as a server or the like, power saving of the whole information processing device is required, and it is a problem in the technical field of the processor to reduce the power consumption of the individual processor included in the information processing device. It is generally known that the power consumption of the semiconductor device such as the processor or the like is proportional to the product of the square of the power supply voltage to be supplied to the circuit inside the semiconductor device and the frequency. Accordingly, to reduce the power consumption of the processor, it is desired to appropriately control the frequency and the voltage. However, due to the individual difference caused by the variation in kind of the processor and semiconductor process manufacturing the processor, the frequency parameter and the voltage parameter suitable of each processor are different. For this reason, to appropriately control the frequency parameter and the voltage parameter, software performing complex control to absorb the variation in the kind of the processor and the semiconductor process is required.